Low power is one of the main desirable features of portable communication appliances and high-speed links. Ideally, zero current consumption in standby or OFF mode greatly contributes to the ‘low power’ tag of a device. In addition to this, low power also refers to the speed and accuracy with which a circuit can resume normal mode of operation. Thus, fast switching is crucial to both, reducing power and enhancing dynamic performance of high-speed links. These links predominantly use current mode transmission and hence their power consumption and dynamic performance is dictated by the high-speed current switching. High-speed switching of large current sources is difficult due to huge parasitic capacitances associated with the circuit.
Settling time taken by the gate bias voltage of the current source when the current source is turned ON/OFF is further delayed by capacitive coupling between gate and drain terminals. Thus, the circuits do not meet the specified signal amplitude and timing specification of standards such as USB 2.0. This leaves designers with two options; either to keep the current source in ON state even in non transmission mode or to design a circuit for faster settling of the current source's bias voltage after switching. The first option makes the circuit power hungry while the design of the circuit as in option two, in itself is a challenge to the designer.
Current Source can be turned OFF by pulling the gate terminal to the supply voltage or by making the output path (or drain terminal), high impedance. Pulling the gate terminal takes a long time to bring the bias voltage to its actual value. So, it needs higher bias current to handle huge capacitance at the gate terminal to keep the settling time within limits. In case of increasing impedance, a sudden change in the drain voltage is coupled to gate, altering the bias voltage. The gate-drain capacitance is at its highest when transistor is operating in deep-linear region. Therefore, when the capacitance starts increasing, coupling at gate can be as high as half the voltage change at drain. This significantly dips down the voltage at gate terminal, giving rise to current higher than actual current.